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Mono CODEC with Speaker Driver
DESCRIPTION
The WM8940 is a low power, high quality mono CODEC designed for portable applications such as digital still cameras or camcorders. The device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. A selectable high pass filter and four fully-programmable notch filters are available in the ADC path. An advanced mixed signal ALC function with noise gate is provided, while readback of PGA gain during ALC operation is supported. The digital audio interface supports Alaw and -law companding. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8940 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. Different sections of the chip can also be powered down under software control using the selectable two or three wire control interface. WM8940 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance.
WM8940
FEATURES
* * * * * * * * * Mono CODEC: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 98dB, THD -84dB (`A'-weighted @ 8 - 48ks/s) ADC SNR 94dB, THD -80dB (`A'-weighted @ 8 - 48ks/s) On-chip Headphone/Speaker Driver - 40mW output power into 16 - BTL speaker drive 0.4W into 8 Additional MONO Line output Multiple analog or `Aux' inputs, plus analog bypass path Mic Preamps: Differential or single end Microphone Interface - Programmable preamp gain - Pseudo differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones
*
OTHER FEATURES * Digital Playback Limiter * Programmable high pass filter (wind noise reduction) * 4 notch filters (narrowband noise suppression) * On-chip PLL * Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) * 4x4x0.9mm 24 lead QFN package
APPLICATIONS
* * Digital still cameras and camcorders General purpose mono audio CODEC
WOLFSON MICROELECTRONICS plc
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Pre-Production, Rev 3.0, February 2007,
Copyright (c)2007 Wolfson Microelectronics plc
WM8940 BLOCK DIAGRAM
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WM8940 TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION...........................................................................................5 ORDERING INFORMATION ..................................................................................5 PIN DESCRIPTION ................................................................................................6 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8
TERMINOLOGY .......................................................................................................... 10
POWER CONSUMPTION ....................................................................................11 SIGNAL TIMING REQUIREMENTS .....................................................................12
SYSTEM CLOCK TIMING ........................................................................................... 12 AUDIO INTERFACE TIMING - MASTER MODE ........................................................ 12 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 13 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 14 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 15
DEVICE DESCRIPTION.......................................................................................16
INTRODUCTION ......................................................................................................... 16 INPUT SIGNAL PATH ................................................................................................. 17 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 22 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 27 OUTPUT SIGNAL PATH ............................................................................................. 40 ANALOGUE OUTPUTS............................................................................................... 44 OUTPUT SWITCH ...................................................................................................... 47 DIGITAL AUDIO INTERFACES................................................................................... 50 AUDIO SAMPLE RATES ............................................................................................. 54 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 54 COMPANDING............................................................................................................ 57 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 59 CONTROL INTERFACE.............................................................................................. 59 3-WIRE SERIAL CONTROL MODE ............................................................................ 61 READBACK IN 3-WIRE MODE ................................................................................... 61 2-WIRE SERIAL CONTROL MODE ............................................................................ 62 RESETTING THE CHIP .............................................................................................. 62 POWER SUPPLIES .................................................................................................... 62 POWER MANAGEMENT ............................................................................................ 64 POP MINIMISATION ................................................................................................... 65
REGISTER MAP...................................................................................................66
REGISTER BITS BY ADDRESS ................................................................................. 67
DIGITAL FILTER CHARACTERISTICS ...............................................................78
TERMINOLOGY .......................................................................................................... 78 DAC FILTER RESPONSES......................................................................................... 79 ADC FILTER RESPONSES......................................................................................... 79 HIGHPASS FILTER..................................................................................................... 80 NOTCH FILTERS AND LOW PASS FILTER............................................................... 81
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NOTCH FILTER WORKED EXAMPLE........................................................................ 82
APPLICATIONS INFORMATION .........................................................................83
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 83
PACKAGE DIAGRAM ..........................................................................................84 IMPORTANT NOTICE ..........................................................................................85
ADDRESS ................................................................................................................... 85
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WM8940
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE WM8940GEFL/V WM8940GEFL/RV Note: Reel Quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 24-lead QFN (4x4x0.9mm) (Pb-free) 24-lead QFN (4x4x0.9mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PACKAGE BODY TEMPERATURE 260oC 260oC
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WM8940 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME MICBIAS AVDD AGND DCVDD DBVDD DGND ADCDAT DACDAT FRAME BCLK MCLK CSB/GPIO SCLK SDIN MODE / GPIO MONOOUT SPKOUTP SPKGND SPKOUTN SPKVDD AUX VMID MICN MICP Supply Supply Supply Supply Supply Digital Output Digital Input Digital Input / Output Digital Input / Output Digital Input Digital Input / Output Digital Input Digital Input / Output Digital Input Analogue Output Analogue Output Supply Analogue Output Supply Analogue Input Reference Analogue Input Analogue Input TYPE Analogue Output Microphone bias Analogue supply Analogue ground Digital Supply (Core) Digital supply (Input/Output) Digital ground ADC digital audio data output DAC digital audio data input DAC and ADC sample rate clock or frame synch Digital audio port clock Master clock input 3-Wire control interface chip select or GPIO pin. DESCRIPTION
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3-Wire control interface clock Input / 2-Wire control interface clock input 3-Wire control interface data Input / 2-Wire control interface data input Control interface mode selection pin or GPIO pin. Mono output Speaker output positive Speaker ground Speaker output negative Speaker supply Auxiliary analogue input Decoupling for midrail reference voltage Microphone negative input (common mode) Microphone positive input
Note: 1. 2. It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to the application note WAN_0118 on "Guidelines on How to Use QFN Packages and Create Associated PCB Footprints"
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WM8940
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD, SPKVDD supply voltages Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Notes 1. 2. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. MIN -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +4.2 DVDD +0.3V AVDD +0.3V +85C +150C
30C max / 85% RH max
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Ground Notes 1. 2. Analogue supply voltages must not be less than the digital supply voltages DBVDD should not be < DCVDD SYMBOL DCVDD DBVDD AVDD, SPKVDD1 DGND,AGND, SPKGND TEST CONDITIONS MIN 1.71 1.71 2.5 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
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WM8940 ELECTRICAL CHARACTERISTICS
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Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level - Singleended input via LIN/RIN 1 Full-scale Input Signal Level - Pseudo-differential input 1,2 Input PGA equivalent input noise INPPGAVOL = +35.25dB No input signal 0 to 20kHz INPPGAVOL = +35.25dB INPPGAVOL = 0dB INPPGAVOL = -12dB All gain settings All analogue input pins Gain adjusted by INPPGAVOL Guaranteed monotonic INPPGAMUTE PGABOOST= 0 PGABOOST = 1 -12 0.75 108 0 +20 AVDD/3.3 Input boost and mixer enabled, at 0dB gain All analogue Inputs Gain adjusted by AUX2BOOSTVOL -12 3 20 10 +6 AVDD/3.3 AVDD*0.7/ 3.3 76.5 Vrms Vrms
dB
MICN input resistance MICN input resistance MICN input resistance MICP input resistance Input Capacitance Input PGA Programmable Gain Programmable Gain Step Size Input PGA Mute Attenuation Input Gain Boost Input Gain Boost Auxiliary Analogue Inputs (AUX) Full-scale Input Signal Level 2 Input Resistance Input Capacitance Gain range from AUX input PGA mixers AUXLBOOSTVOL and AUXRBOOSTVOL step size
1.6 47 71 94 10 +35.25
k k k k pF dB dB dB dB dB Vrms k pF dB dB
Analogue to Digital Converter (ADC) - Input from MICN and MICN in differential configuration to input PGA INPPGAVO, PGABOOST and ADCVOL = 0dB Signal to Noise Ratio 3 Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation 6 SNR THD THD+N A-weighted AVDD=3.3V -1dBV Input AVDD=3.3V -1dBV Input AVDD=3.3V 1kHz full scale input signal 91 -83 -77 100 dB dB dB dBFS
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WM8940
Digital to Analogue Converter (DAC) to MONO Output with 10k / 50pF load and DACVOL 0dB Full-scale output 1 Signal to Noise Ratio
3
DACVOL = 0dB SNR
4
AVDD1/3.3 98 -80 -78 100
Vrms dB dBFS dBFS dB
A-weighted AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=3.3V 1kHz signal
Total Harmonic Distortion
THD THD+N
Total Harmonic Distortion + Noise 5 Channel Separation 6
MICP and MICN input PGA to input boost stage into 10k / 50pF load on SPKOUTP and SPKOUTP INPPGAVOL, PGABOOST = 0dB Full-scale output voltage, 0dB gain Signal to Noise Ratio
3
AVDD2/3.3 SNR A-weighted AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=3.3V 98 -80 -78 100
Vrms dB dBFS dBFS dB
Total Harmonic Distortion
4
THD THD+N
Total Harmonic Distortion + Noise 5 Channel Separation 6
Speaker Output (SPKOUTP, SPKOUTN with 8 bridge tied load) Output Power Total Harmonic Distortion 4 Po THD Output power is closely correlated with THD see below Po=150mW, RL = 8 SPKVDD=3.3V Po=350mW, RL = 8 SPKVDD=3.3V Signal to Noise Ratio 3 Power Supply Rejection Ratio (50Hz-22kHz) Signal to Noise Ratio 3 Total Harmonic Distortion Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input Capacitance VIH VIL VOH VOL IOL=1mA IOH-1mA All digital pins 10 0.9x DBVDD 0.1xDBVDD 0.7x DBVDD 0.3xDBVDD V V V V pF MBVSEL=0 MBVSEL=1 for VMICBIAS within +/-3% 1kHz to 20kHz 15 0.9*AVDD1 0.65*AVDD1 3 V V Ma nV/Hz
4
0.03 -68 2.944 -30.6 98 50
% dB % dB dB dB
SNR PSRR
A-weighted SPKVDD=3.3V RL = 8 BTL
Headphone Output (SPKOUTP, SPKOUTN with resistive load to GND) SNR THD A-weighted SPKVDD=3.3V Po=20mW, RL = 16 SPKVDD=3.3V 98 0.02 -72 dB % dB
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WM8940
TERMINOLOGY
1.
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Full-scale input and output levels scale in relation to AVDD or AVDD2 depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1Vrms (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD. Input level to RIP and LIP in differential configurations is limited to a maximum of -3dB or performance will be reduced. Signal-to-noise ratio (dB) - SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). Total Harmonic Distortion (dB) - THD is the difference in level between a reference output signal and the first seven harmonics of that signal. The reference output signal need not be at full scale amplitude; THD is typically measured using an output power of 20mW into a 16ohm load, corresponding to a reference signal level of -5dB. However the stated test conditions include input signal level, signal gain settings, output load characteristics and power supply voltages To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. THD is the difference in level between a reference output signal and the first seven harmonics of the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. Total Harmonic Distortion plus Noise (dB) - THD+N is the difference in level between a reference output signal and the sum of the harmonics, wide-band noise and interference on the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the total harmonics, wide-band noise and interference is calculated. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down
2. 3.
4.
5.
6.
7.
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WM8940
POWER CONSUMPTION
Typical current consumption for various scenarios is shown below. DCVDD (1.8V) MA 0 0 0.3 1.9 1.6 1.6 1.8 DBVDD (1.8V) UA 0.2 0.2 11 115 3.7 3.8 81 TOTAL POWER (MW) 0.126 0.627 14.3 21.0 17.1 216.8 21.1
MODE Power OFF (No Clocks) Sleep (VMID maintained, No Clocks) Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE Mono Record (MIC input, +20dB gain, 44.1kHz, PLL, quiescent) MASTER Mono 16 Headphone Playback (0.1mW, 1kHz sine wave, ac coupled) SLAVE Mono 8 BTL speaker Playback (44.1kHz, 200mW, 1kHz sine wave) SLAVE Mono 8 BTL speaker Playback (44.1kHz, PLL, quiescent) MASTER Table 1 Power Consumption
AVDD (3V3) MA 0.038 0.190 4.1 5.3 2.8 2.8 3.9
SPKVDD (3V3) MA 0 0 0 0 1.5 62 1.5
Note: Power consumption figures include any power dissipated in the load (e.g. in the headphone or speaker)
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WM8940 SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
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Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. TMCLKY TMCLKDS MCLK=SYSCLK (=256fs) MCLK input to PLL Note 1 81.38 20 60:40 40:60 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
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WM8940
Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 15 ns ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low FRAME set-up time to BCLK rising edge FRAME hold time from BCLK rising edge DACDAT hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDS tDD 81.38 32.55 32.55 10 10 10 10 15 ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8940
CONTROL INTERFACE TIMING - 3-WIRE MODE
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Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8940
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t8 t5 t3
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8940 DEVICE DESCRIPTION
INTRODUCTION
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The WM8940 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or camcorders with mono audio, record and playback capability.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. These inputs have a user programmable gain range of -12dB to +35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a further 20dB of gain. A microphone bias is output from the chip which can be used to bias the microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
AUX INPUT
The device includes a mono input, AUX, that can be used as an input for warning tones (beep) etc. The output from this circuit can be summed into the mono output and/or the speaker output paths, so allowing for mixing of audio with `backing music' etc as required. This path can also be summed into the input in a flexible fashion, either to the input PGA as a second microphone input or as a line input. The configuration of this circuit, with integrated on-chip resistors allows several analogue signals to be summed into the single AUX input if required. ADC The mono ADC uses a multi-bit high-order over sampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable mono audio type applications.
DIGITAL FILTERING
Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. Application specific digital filters are also available which help to reduce the effect of specific noise sources such as wind noise or narrowband noise from other parts of the system. The filters include a programmable ADC high pass filter and four fully programmable ADC notch filters.
OUTPUT MIXING AND VOLUME ADJUST
Flexible mixing is provided on the outputs of the device; a mixer is provided for the speaker outputs, and an additional mono summer for the mono output. These mixers allow the output of the DAC, the output of the ADC volume control and the Auxiliary input to be combined. The output volume can be adjusted using the integrated digital volume control and there is additional analogue gain adjustment capability on the speaker output.
AUDIO INTERFACES
The WM8940 has a standard audio interface, to support the transmission of audio data to and from the chip. This interface is a 4 wire standard audio interface which supports a number of audio data 2 formats including I S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.
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WM8940
CONTROL INTERFACES
To allow full software control over all its features, the WM8940 supports 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2wire control mode is selected. In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8940 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC/ADC. However, a PLL is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the CLKOUT pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8940 has given much attention to power consumption without compromising performance. It operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control. As a power saving measure, ADC or DAC logic in the DSP core is held in its last enabled state when the ADC or DAC is disabled. In order to prevent pops and clicks on restart due to residual data in the filters, the master clock must remain for at least 64 input samples after the ADC or DAC has been disabled.
INPUT SIGNAL PATH
The WM8940 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block which then feeds into a gain boost/mixer stage.
MICROPHONE INPUTS
The WM8940 can accommodate a variety of microphone configurations including single ended and differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through the input PGA as shown in Figure 6 . A pseudo differential input is the preferential configuration where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when AUX2INPPGA=1) input pins. Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting MICP2INPPGA to 0. In pseudo-differential mode the larger signal should be input to MICP and the smaller (e.g. noisy ground connections) should be input to MICN.
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Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input)
REGISTER ADDRESS R44 Input Control
BIT 2
LABEL AUX2INPPGA 0
DEFAULT
DESCRIPTION Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string
1
MICN2INPPGA
1
0
MICP2INPPGA
0
Table 2 Input Control The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPPGAEN DEFAULT 0 DESCRIPTION Input microphone PGA enable 0 = disabled 1 = enabled
Table 3 Input PGA Enable Control
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Pre-Production INPUT PGA VOLUME CONTROL
WM8940
The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the MICP pin when MICP2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled automatically and the INPPGAVOL bits should not be used. REGISTER ADDRESS R45 Input PGA volume control 7 BIT LABEL INPPGAZC DEFAULT 0 DESCRIPTION Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain)
6
INPPGAMUTE
1
5:0
INPPGAVOL
010000
R32 8 ALC control 1
ALCSEL
0
Table 4 Input PGA Volume Control
AUXILLIARY INPUT
An auxiliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. The circuit is enabled by the register bit AUXEN.
Figure 7 Auxiliary Input Circuit
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The AUXMODE register bit controls the auxiliary input mode of operation:
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In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the aux circuit using only the internal components. In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20k resistors relative to the higher tolerance external resistors. REGISTER ADDRESS R1 Power management 1 R44 Input control 6 BIT LABEL AUXEN DEFAULT 0 DESCRIPTION Auxiliary input buffer enable 0 = OFF 1 = ON 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed)
3
AUXMODE
0
Table 5 Auxiliary Input Buffer Control
INPUT BOOST
The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 8.
Figure 8 Input Boost Stage The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0) or be completely isolated from the input boost circuit (INPPGAMUTE=1).
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REGISTER ADDRESS R45 6 Input PGA gain control R47 Input BOOST control 8 BIT LABEL INPPGAMUTE DEFAULT 1 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
PGABOOST
0
Table 6 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. REGISTER ADDRESS R47 Input BOOST control BIT 6:4 LABEL MICP2BOOSTVOL DEFAULT 000 DESCRIPTION Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
2:0
AUX2BOOSTVOL
000
Table 7 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTEN DEFAULT 0 DESCRIPTION Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
Table 8 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit.
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REGISTER ADDRESS R1 Power management 1 4 BIT LABEL MICBEN DEFAULT 0
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DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 9 Microphone Bias Enable
REGISTER ADDRESS R44 Input Control 8
BIT
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD
Table 10 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
VMID internal resistor internal resistor
MB
MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD
AGND
Figure 9 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8940 uses a multi-bit, over sampled sigma-delta ADC channel. The use of multi-bit feedback and high over sampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit over sampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in .
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Figure 10 ADC Digital Filter Path The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS R2 Power management 2 Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit. REGISTER ADDRESS R14 ADC Control 0 BIT LABEL ADCPOL DEFAULT 0 DESCRIPTION 0=normal 1=inverted 0 BIT LABEL ADCEN DEFAULT 0 DESCRIPTION 0 = ADC disabled 1 = ADC enabled
Table 12 ADC Polarity
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14. REGISTER ADDRESS R14 ADC Control 8 BIT LABEL HPFEN DEFAULT 1 DESCRIPTION High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 14 for details.
7
HPFAPP
0
6:4 Table 13 ADC Filter Select
HPFCUT
000
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HPFCUT SR=101/100 8 000 001 010 011 100 101 110 111 82 102 131 163 204 261 327 408 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408 FS (KHZ) SR=011/010 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408
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SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 14.
PROGRAMMABLE NOTCH FILTERS
Four programmable notch filters are provided. These filters have a programmable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFx_A0[13:0] and NFx_A1[13:0]. Notch Filter 3 can also be programmed as a 1st order low pass filter. Because these coefficient values require two register writes to set up there is an NFx_UP (Notch Filter Update) flag for each filter which should be set only when both A0 and A1 for the filter have been set. The notch filters can be individually enabled, using the corresponding NFx_EN register bit, as can be seen in Figure 11.
Figure 11 Labelling of Notch Filters and Arrangement of Notch Filter Enables
REGISTER ADDRESS R16 Notch Filter 0A
BIT 15
LABEL NF0_UP
DEFAULT 0
DESCRIPTION Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. Notch filter 0 enable: 0=Disabled 1=Enabled
14
NF0_EN
0
13:0 R17 Notch Filter 0B 15
NF0_A0 NF0_UP
0 0
Notch Filter 0 a0 coefficient Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. Notch Filter 0 a1 coefficient
13:0
NF0_A1
0
Table 15 Notch Filter 0 Function
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Pre-Production REGISTER ADDRESS R18 Notch Filter 1A BIT 15 LABEL NF1_UP DEFAULT 0
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DESCRIPTION Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. 14 NF1_EN 0 Notch Filter 1 enable. 0=Disabled 1=Enabled Notch Filter 1 a0 coefficient Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. 13:0 NF1_A1 0 Notch Filter 1 a1 coefficient Table 16 Notch Filter 1 Function
13:0 R19 Notch Filter 1B 15
NF1_A0 NF1_UP
0 0
REGISTER ADDRESS R20 Notch Filter 2A
BIT 15
LABEL NF2_UP
DEFAULT 0
DESCRIPTION Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. Notch Filter 2 enable. 0=Disabled 1=Enabled Notch Filter 2 a0 coefficient Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. Notch Filter 2 a1 coefficient
14
NF2_EN
0
13:0 R21 Notch Filter 2B 15
NF2_A0 NF2_UP
0 0
13:0
NF2_A1
0
Table 17 Notch Filter 2 Function
REGISTER ADDRESS R22 Notch Filter 3A
BIT 15
LABEL NF3_UP
DEFAULT 0
DESCRIPTION Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. Notch Filter 3 enable. 0=Disabled 1=Enabled Notch Filter 3 a0 coefficient Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. Notch Filter 3 mode select 0 = Notch Filter mode 1 = Low Pass Filter mode Notch Filter 3 a1 coefficient
14
NF3_EN
0
13:0 R23 Notch Filter 3B 15
NF3_A0 NF3_UP
0 0
14
NF3_LP
0
13:0
NF3_A1
0
Table 18 Notch Filter 3 Function The notch filter coefficients must be entered using a sign / magnitude notation. The MSB of the 14bit register word (NFx_Ax[13]) is reserved for the sign part, leaving the 13 remaining bits for the magnitude part. The notch filter coefficients are calculated as follows:
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a0 = 1 - tan( wb / 2) 1 + tan( wb / 2)
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a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s
wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The actual register values can be determined from the coefficients as follows: NFn_A0 = -a0 x 213 NFn_A1 = -a1 x 212 To configure Notch Filter 3 as a 1st order low pass filter, set the NF3_LP bit to 1 and calculate the coefficients as follows:
a0 = 0
a1 =
Where:
tan( wc / 2) - 1 tan( wc / 2) + 1
wc = 2f c / f s
fc = cutoff frequency in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NF3_A0 = 0 NF3_A1 = -a1 x212
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x (x-255) dB for 1 x 255, MUTE for x = 0 REGISTER ADDRESS R15 ADC Digital Volume BIT 7:0 LABEL ADCVOL [7:0] DEFAULT 11111111 ( 0dB ) DESCRIPTION ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 19 ADC Volume
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The WM8940 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL.
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
REGISTER ADDRESS
BIT
LABEL ALCMIN [2:0]
DEFAULT 000 (-12dB)
DESCRIPTION Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB ALC function select 0 = ALC disabled 1 = ALC Enabled ALC target - sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS 1011 = -6dBFS 1010 = -7.5dBFS 1001 = -9dBFS 1000 = -10.5dBFS 0111 = -12dBFS 0110 = -13.5dBFS 0101 = -15dBFS 0100 = -16.5dBFS 0011 = -18dBFS 0010 = -19.5dBFS 0001 = -21dBFS 0000 = -22.5dBFS
R32 (20h) 2:0 ALC Control 1
5:3
ALCMAX [2:0]
111 (+35.25dB)
8
ALCSEL
00
3:0 R33 (21h) ALC Control 2
ALCLVL [3:0]
1011 (-6dB)
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REGISTER ADDRESS BIT 7:4 LABEL ALCHLD [3:0] DEFAULT 0000 (0ms)
Pre-Production DESCRIPTION ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 0011 (5.8ms/6dB) 410us 820us 1.64ms 420ms Per 6dB 3.38ms 6.56ms 13.1ms 3.36s 90% of range 23.6ms 47.2ms 94.5ms 24.2s
R34 (22h) 8 ALC Control 3 7:4
ALCMODE
0
ALCDCY [3:0]
0011 (26ms/6dB)
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 1010 90.8us 182us 363us 93ms Per 6dB 726us 1.45ms 2.91ms 744ms 90% of range 5.23ms 10.5ms 20.9ms 5.36s
... (time doubles with every step) 3:0 ALCATK [3:0] 0010 (3.3ms/6dB) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 104us 208us 416us Per 6dB 832us 1.66ms 3.33ms 852ms 90% of range 6ms 12ms 24ms 6.13s
... (time doubles with every step) 1010 or 106ms higher 0010 (726us/6dB)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 22.7us 45.4us 90.8us Per 6dB 182.4us 363us 726us 90% of range 1.31ms 2.62ms 5.23ms
... (time doubles with every step)
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Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT 1010 or higher R42 (2Ah) 1 ALC Control 4 ALCZC 0 (zero cross off) DESCRIPTION 23.2ms 186ms
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1.34s
ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled
Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this.
Figure 12 ALC Normal Mode Operation
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WM8940 LIMITER MODE
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In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode.
Figure 13 ALC Limiter Mode Operation
ATTACK AND DECAY TIMES
The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register).
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NORMAL MODE
ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATK 104s 208s 416s 832s 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms Attack Time (s) tATK6dB tATK90% 832s 6ms 1.66ms 12ms 3.33ms 24ms 6.66ms 48ms 13.3ms 96ms 26.6ms 192ms 53.2ms 384ms 106ms 767ms 213.2ms 1.53s 426ms 3.07s 852ms 6.13s
ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCY 410s 820s 1.64ms 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms Decay Time (s) tDCY6dB tDCY90% 3.28ms 23.6ms 6.56ms 47.2ms 13.1ms 94.5ms 26.2ms 189ms 52.5ms 378ms 105ms 756ms 210ms 1.51s 420ms 3.02s 840ms 6.05s 1.68s 12.1s 3.36s 24.2s
Table 21 ALC Normal Mode (Attack and Decay times)
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LIMITER MODE
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ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATKLIM 22.7s 45.4S 90.8S 182S 363S 726S 1.45ms 2.9ms 5.81ms 11.6ms 23.2ms Attack Time (s) tATKLIM6dB tATKLIM90% 182s 1.31ms 363s 2.62ms 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s
ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCYLIM 90.8s 182S 363S 726S 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms Attack Time (s) tDCYLIM6dB tDCYLIM90% 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s 372ms 2.68s 744ms 5.36s
Table 22 ALC Limiter Mode (Attack and Decay times)
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MINIMUM AND MAXIMUM GAIN
The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
REGISTER ADDRESS
BIT
LABEL ALCMAX ALCMIN
DEFAULT 111 000
DESCRIPTION Set Maximum Gain of PGA Set minimum gain of PGA
R32 5:3 ALC Control 1 2:0
Table 23 ALC Max/Min Gain
In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal.
Figure 14 ALC Min/Max Gain
ALCMAX 111 110 101 100 011 010 001 000
Maximum Gain (dB) 35.25 29.25 23.25 17.25 11.25 5.25 -0.75 -6.75
Table 24 ALC Max Gain Values
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ALCMIN 000 001 010 011 100 101 110 111 Minimum Gain (dB) -12 -6 0 6 12 18 24 30
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Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits.
ALC HOLD TIME (NORMAL MODE ONLY)
In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD register.
REGISTER ADDRESS
BIT
LABEL ALCHLD
DEFAULT 0000
DESCRIPTION ALC hold time before gain is increased.
R33 7:4 ALC Control 2
Table 26 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation.
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Figure 15 ALCLVL
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Figure 16 ALC Hold Time
ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
tHOLD (s) 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s
Table 27 ALC Hold Time Values
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PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE (NORMAL MODE ONLY)
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8940 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS R35 (23h) ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -69dB 110 = -75dB 111 = -81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 28 ALC Noise Gate Control
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The diagrams below show the response of the system to the same signal with and without noise gate.
Figure 17 ALC Operation Above Noise Gate Threshold
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Figure 18 Noise Gate Operation
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OUTPUT SIGNAL PATH
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The WM8940 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit DACEN. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8940, irrespective of whether the DACs are running or not. The WM8940 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control A digital peak limiter. Sigma-Delta Modulation The high performance sigma-delta audio DAC converts the digital data into an analogue signal.
DAC DIGITAL FILTERS
DIGITAL AUDIO INTERFACE DIGITAL GAIN DIGITAL PEAK LIMITER DIGITAL FILTERS INTERP SDM DAC
Figure 19 DAC Digital Filter Path The analogue output from the DAC can then be mixed with the AUX analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: can drive a 16 or 32 headphone or line output or can be a buffered version of VMID (When MONOMUTE=1). SPKOUTP/N: can drive a 16 or 32 stereo headphone or stereo line output, or an 8 BTL mono speaker.
DIGITAL HI-FI DAC VOLUME CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; REGISTER ADDRESS R11 DAC Digital Volume BIT 7:0 LABEL DACVOL [7:0] MUTE for X = 0 DEFAULT 11111111 ( 0dB ) DESCRIPTION DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 29 DAC Volume
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HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC)
The DAC is enabled by the DACEN register bit. REGISTER ADDRESS R3 Power Management 3 Table 30 DAC Enable The WM8940 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will step back up to the digital gain setting. This function is disabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero. 0 BIT LABEL DACEN DEFAULT 0 DESCRIPTION DAC enable 0 = DAC disabled 1 = DAC enabled
REGISTER ADDRESS R10 DAC Control
BIT 6
LABEL DACMU 0
DEFAULT
DESCRIPTION DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled
Table 31 DAC Control Register The digital audio data is converted to over sampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bit stream data enters a multi-bit, sigma-delta DAC, which converts it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. The DAC output defaults to non-inverted. Setting DACPOL will invert the DAC output phase.
AUTOMUTE
The DAC has an automute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Automute can be enabled using the AMUTE control bit. REGISTER ADDRESS R10 DAC Control BIT 2 LABEL AMUTE 0 DEFAULT DESCRIPTION DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled
Table 32 DAC Auto Mute Control Register
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DAC OUTPUT LIMITER
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The WM8940 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
Figure 20 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 33, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value. VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
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REGISTER ADDRESS R24 8 DAC digital limiter control 1 7:4 BIT LABEL LIMEN 0 DEFAULT DESCRIPTION Enable the DAC digital limiter: 0=disabled 1=enabled Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 3:0 LIMATK 0010 1011 to 1111=1.536s Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 6:4 R25 DAC digital limiter control 2 LIMLVL 000 Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB
LIMDCY
0011
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REGISTER ADDRESS BIT 3:0 LABEL LIMBOOST DEFAULT 0000
Pre-Production DESCRIPTION Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved Table 33 DAC Digital Limiter Control
ANALOGUE OUTPUTS
The WM8940 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1V rms signals.
SPKOUTP/SPKOUTN OUTPUTS
The SPKOUT pins can drive a single bridge tied 8 speaker or two headphone loads of 16 or 32 or a line output (see Headphone Output and Line Output sections, respectively). The signal to be output on SKPKOUT comes from the Speaker Mixer circuit and can be any combination of the DAC output, the Bypass path (output of the boost stage) and the AUX input. The SPKOUTP/N volume is controlled by the SPKVOL register bits. Note that gains over 0dB may cause clipping if the signal is large. The SPKMUTE register bit causes the speaker outputs to be muted (the output DC level is driven out). The output pins remains at the same DC level (VMIDOP), so that no click noise is produced when muting or un-muting. The SPKOUTN pin always drives out an inverted version of the SPKOUTP signal. REGISTER ADDRESS R50 Speaker mixer control 5 BIT LABEL AUX2SPK DEFAULT 0 DESCRIPTION Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of DAC to speaker mixer input 0 = not selected 1 = selected Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB
1
BYP2SPK
0
0
DAC2SPK
0
R54 Bypass path attenuation control
8
SPKATTN
0
Table 34 Speaker Mixer Control
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REGISTER ADDRESS R54 Speaker volume control 7 BIT LABEL SPKZC DEFAULT 0 DESCRIPTION Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB
6
SPKMUTE
1
5:0
SPKVOL [5:0]
111001 (0dB)
Table 35 SPKOUT Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is either 31Hz or 47Hz.
REGISTER ADDRESS R7 Additional control 0
BIT
LABEL SLOWCLKEN
DEFAULT 0
DESCRIPTION Slow clock enable. Used for both the jack insert detect de-bounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled
Table 36 Timeout Clock Enable Control
MONO MIXER AND OUTPUT
The MONOOUT pin can drive a 16 or 32 headphone or a line output or be used as a DC reference for a headphone output (see Headphone Output section). It can be selected to drive out any combination of DAC, Bypass (output of input BOOST stage) and AUX. This output is enabled by setting bit MONOEN.
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REGISTER ADDRESS R56 Mono mixer control BIT 7 LABEL MONOATTN DEFAULT 0
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DESCRIPTION Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Output of Auxilary amplifier to mono mixer input: 0 = not selected 1 = selected Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Output of DAC to mono mixer input 0 = not selected 1 = selected
6
MONOMUTE
0
2
AUX2MONO
0
1
BYP2MONO
0
0
DAC2MONO
0
Table 37 Mono Mixer Control
ENABLING THE OUTPUTS
Each analogue output of the WM8940 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8940 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see "POP Minimisation" section).
REGISTER ADDRESS R1 Power management 1 R3 Power management 3 3 2 7 6 5 3 2
BIT
LABEL BIASEN BUFIOEN MONOEN SPKNEN SPKPEN SPKMIXEN 0 0 0 0 0 0
DEFAULT
DESCRIPTION Analogue amplifiers bias enable VMID buffer enable MONOOUT enable SPKOUTN enable SPKOUTP enable Mono mixer enable Speaker Mixer enable
MONOMIXEN 0
Note: All "Enable" bits are 1 = ON, 0 = OFF Table 38 Output Stages Power Management Control
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k.
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REGISTER ADDRESS R49 0 BIT LABEL VROI 0 DEFAULT DESCRIPTION VREF (AVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k
Table 39 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. Table 40 summarises the tie-off options for the speaker and mono output pins.
Figure 21 Unused Input/Output Pin Tie-off Buffers MONOEN/ SPKN/PEN 0 0 1 VROI 0 1 X OUTPUT CONFIGURATION 1k tieoff to AVDD/2 30k tieoff to AVDD/2 Output enabled (DC level=AVDD/2)
Table 40 Unused Output Pin Tie-off Options
OUTPUT SWITCH
When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. As an example when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001, pin CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the polarity of the CSB/GPIO input pin. Note that the speaker outputs and the mono output must be enabled for this function to work (see Table 41). The CSB/GPIO pin has an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK, enabled using the SLOWCLKEN register bit.
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GPIOPOL CSB/GPIO SPKNEN/ SPKPEN 0 1 X X X X 0 1 X X 0 1 0 1 X X MONOEN SPEAKER ENABLED No Yes No No No No No Yes
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MONO OUTPUT ENABLED No No No Yes No Yes No No
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Table 41 Output Switch Operation (GPIOSEL=001)
THERMAL SHUTDOWN
The speaker outputs can drive very large currents. To protect the WM8940 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125oC. See General Purpose Input/Output section.
REGISTER ADDRESS R49 Output control 1
BIT
LABEL TSDEN 1
DEFAULT
DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 42 Thermal Shutdown
SPEAKER OUTPUT
SPKOUTP/N can differentially drive a mono 8 Bridge Tied Load (BTL) speaker as shown below.
Figure 22 Speaker Output Connection
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HEADPHONE OUTPUT
The speaker outputs can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor.
Headphone Output using DC Blocking Capacitors:
DC Coupled Headphone Output:
Figure 23 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the MONOOUT pin. The MONOOUT pin can be configured as a DC output driver by setting the MONOMUTE register bit. The DC voltage on MONOOUT in this configuration is equal to the DC offset on the SPROUTP and SPKOUTN pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
MONO OUTPUT
The mono output, can be used as a line output, a headphone output or as a pseudo ground for capless driving of loads by SPKOUT. Recommended external components are shown below.
Figure 24 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1 = 1F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 will diminish the bass response. The function of R1 is to protect the line outputs from damage when used improperly.
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DIGITAL AUDIO INTERFACES
The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input FRAME: Data alignment clock BCLK: Bit clock, for synchronisation
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The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: * * * * Left justified Right justified IS DSP mode A / B
2
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8940 audio interface may be configured as either master or slave. As a master interface device the WM8940 generates BCLK and FRAME and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8940 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 25 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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Figure 26 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 27 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (Mode B) the 2nd (Mode A) rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. FRAMEP should be set to 0 in this mode.
Figure 28 DSP/PCM Mode Audio Interface (Mode A, FRAMEP=0)
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1/fs 1 BCLK 1 BCLK falling edge can occur anywhere in this area
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LRC
BCLK
LEFT CHANNEL DACDAT / ADCDAT
1 2 3 n-2 n-1 n 1 2
RIGHT CHANNEL
3 n-2 n-1 n
MSB
Input Word Length (WL)
LSB
Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
REGISTER ADDRESS R4 Audio interface control 9
BIT
LABEL LOUTR
DEFAULT 0
DESCRIPTION LOUTR control 0=normal 1=Input mono channel data output on both left and right channels BCLK polarity 0=normal 1=inverted Frame clock polarity (for RJ, LJ and I2S formats) 0=normal 1=inverted DSP Mode control 1 = Configures interface so that MSB is available on 1st BCLK rising edge after FRAME rising edge 0 = Configures interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge Word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) Audio interface Data Format Select: 00=Right Justified 01=Left Justified 2 10=I S format 11= DSP/PCM mode
8
BCP
0
7
FRAMEP
0
6:5
WL
10
4:3
FMT
10
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Pre-Production REGISTER ADDRESS 2 BIT LABEL DLRSWAP DEFAULT 0
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DESCRIPTION Controls whether DAC data appears in `right' or `left' phases of FRAME clock: 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME 8 Bit Word Length Enable Only recommended for use with companding 0=Word Length controlled by WL 1=8 bits
1
ALRSWAP
0
R5 Companding Control
5
WL8
0
Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. REGISTER ADDRESS R6 Clock generation control 8 BIT LABEL CLKSEL DEFAULT 1 DESCRIPTION Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER)
7:5
MCLKDIV
010
4:2
BCLKDIV
000
0
MS
0
Table 44 Clock Control
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AUDIO SAMPLE RATES
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The WM8940 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
REGISTER ADDRESS R7 Additional control
BIT 3:1 SR
LABEL
DEFAULT 000
DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved
Table 45 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8940 has an on-chip phase-locked loop (PLL) circuit that can be used to: * * Generate master clocks for the WM8940 audio functions from another external clock, e.g. in telecoms applications. Generate an output clock, on pin CSB/GPIO, for another part of the system (derived from an existing audio master clock).
Figure 30 shows the PLL and internal clocking arrangement on the WM8940. The PLL is enabled or disabled by the PLLEN register bit. Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
REGISTER ADDRESS R1 Power management 1 5
BIT
LABEL PLLEN
DEFAULT 0 PLL enable 0=PLL off 1=PLL on
DESCRIPTION
Table 46 PLLEN Control Bit
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Figure 30 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 30) can be set using the register bits PLLK and PLLN. N controls the ratio of the division, and K the fractional part. The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz. The PLL output then passes through a fixed divide by 4, and can also be further divided by MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940 DSP.
REGISTER ADDRESS R36 PLL N value
BIT 7
LABEL PLL_POWERDOWN
DEFAULT 0
DESCRIPTION PLL POWER 0=ON 1=OFF Fractional Divide within the PLL 0=Disabled (Lower Power) 1=Enabled 00 = MCLK input multiplied by 2 (default) 01 = MCLK input not divided (default) 10 = Divide MCLK by 2 before input to PLL 11 = Divide MCLK by 4 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
6
FRACEN
1
5:4
PLLPRESCALE
00
3:0
PLLN
1100
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0 8:0 8:0
PLLK [23:18] PLLK [17:9] PLLK [8:0]
0Ch 093h 0E9h
Table 47 PLL Frequency Ratio Control
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INTEGER N DIVISION
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The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12. If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation. INPUT CLOCK (PLL_IN) 11.2896MHz 12.288MHz DESIRED PLL OUTPUT (PLL_OUT) 90.3168MHz 98.304MHz DIVISION REQUIRED (X) 8 8 FRACTIONAL DIVISION (K) 0 0 INTEGER DIVISION (N) 8 8 SDM 0 0
Table 48 PLL Modes of Operation (Integer N mode)
FRACTIONAL K MODE
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up to 1/224). If these are used then FRAC_EN must be set. The relationship between the required division X, the fractional division K[23:0] and the integer division N[3:0] is: K=2
23
( X - N)
where 0 < (X - N) < 1 and K is rounded to the nearest whole number. For example, if the PLL input clock (PLL_IN) is 13MHz and the desired PLL output clock (PLLCLK) is 98.304MHz then the desired division, X, is 7.561800. So N[3:0] will be 7h and K[23:0] will be 23F400h to produce the desired 98.304MHz clock. The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 49. MCLK (MHz) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 F2 (MHz) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE DIVIDE MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 POSTSCALE DIVIDE (FIXED) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 R N (Hex) 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7 K (Hex) 86C220 3126E8 F28BD4 8FD525 45A1CA D3A06E 6872AF 3D70A3 2DB492 FD809F 1F76F7 EE009E 86C226 3126E8 F28BD4 8FD525 BOAC93 482296
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
Table 49 PLL Frequency Examples
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LOOPBACK
Setting the ADC_LOOPBACK or DAC_LOOPBACK register bit enables digital loopback. When the ADC_LOOPBACK bit is set the output data from the ADC audio interface is fed directly into the DAC data input. When the DAC_LOOPBACK bit is set the output data from the DAC audio interface is fed directly to the input of the ADC audio interface.
COMPANDING
The WM8940 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available. It will override the normal audio interface WL bits to give an 8-bit word length. Refer to Table 43 Audio Interface Control for setting the output word length.
REGISTER ADDRESS R5 Companding control
BIT 6
LABEL DAC_LOOPBACK
DEFAULT 0
DESCRIPTION Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC audio interface output is fed directly into ADC audio interface input. DAC decompanding 00=off 01=reserved 10=-law 11=A-law ADC companding 00=off 01=reserved 10=-law 11=A-law Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input.
4:3
DAC_COMP
0
2:1
ADC_COMP
0
0
ADC_LOOPBACK
0
Table 50 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
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BIT7 SIGN EXPONENT BIT[6:4] MANTISSA BIT[3:0]
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Table 51 8-bit Companded Word Composition
u-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 31 u-Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 32 A-Law Companding
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In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In 3 wire mode, the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit Whichever pin is used for GPIO, it is controlled from the GPIO control register R8. The GPIOSEL bits allow the chosen pin to be configured to perform a variety of useful tasks as shown in Table 57. Note that SLOWCLKEN must be enabled when using the jack detect function. REGISTER ADDRESS R8 GPIO control BIT 5:4 LABEL OPCLKDIV DEFAULT 00 DESCRIPTION PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIO Polarity invert 0=Non inverted 1=Inverted CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=SYSCLK clock o/p 101=PLL lock 110=Reserved 111=Reserved
GENERAL PURPOSE INPUT/OUTPUT
3
GPIOPOL
0
2:0
GPIOSEL
000
Table 52 CSB/GPIO Control
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 57. The WM8940 is controlled by writing to registers through a serial control interface. A control word consists of 24 bits. The first 7 bits (B23 to B16) are address bits that select which control register is accessed. The remaining 16 bits (B15 to B0) are register bits, corresponding to the 16 bits in each control register. MODE Low Hi-Z High INTERFACE FORMAT 2 wire 3 wire 3 wire
Table 53 Control Interface Mode Selection
USE OF MODE AS A GPIO PIN IN 3-WIRE MODE
In 3-wire mode, MODE can be used as a GPIO pin. If MODE is being used as a GPIO output, the partner device doesn't have to drive MDE - the pin will be pulled-up internally causing 3-wire mode will be selected. The GPIO function is enabled by setting the MODE_GPIO register bit. The MODE pin can then be controlled using the GPIO register bits as described in [add as xreference]. To use MODE as a GPIO input, MODE must be undriven or driven high at start-up. Specifically MODE must be high or hi-Z during an initial write to the control interface which sets the MODE_GPIO register bit. After MODE_GPIO has been set, 3-wire mode selection is overridden internally and the MODE pin can be used freely as a GPIO input or output.
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Figure 33 Example Usage of MODE Pin to Generate a Clock out in 3-wire Mode This example shows how the MODE_GPIO register bit interfaces to the MODE pad in the case there MODE is used as a GPIO output. When MODE_GPIO is set, the internal version of MODE is overridden to high and the MODE pin output driver is enabled. The pull up, which is used to default 3-wire mode at start-up, is disabled as a power saving measure. MODE_GPIO cannot be set in 2-wire m-de - this would prevent correct operation of the control interface. Internal timing is arranged to ensure that the override is in place before the pull-up is disabled.
REGISTER ADDRESS R8 GPIO control 7
BIT
LABEL MODE_GPIO
DEFAULT 0
DESCRIPTION Selects MODE as a GPIO pin 0 = MODE is an input. MODE selects 2wire mode when low and 3-wire mode when high. 1 = MODE can be an input or output under the control of the GPIO control register. Interface operates in 3-wire mode regardless of what happens on the MODE pin.
Table 54 Mode is GPIO Control Auto-incremental writes are supported in 2 wire and 3 wire modes. This is enabled by default. REGISTER ADDRESS R9 Control Interface 1 BIT LABEL AUTOINC DEFAULT 1 DESCRIPTION Auto-Incremental write enable 0=Auto-Incremental writes disabled 1=Auto-Incremental writes enabled
Table 55 Control Interface
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In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
3-WIRE SERIAL CONTROL MODE
Figure 34 3-Wire Serial Control Interface
READBACK IN 3-WIRE MODE
The following two timing diagrams are also supported.
Figure 35 Alternative 3-Wire Serial Control Timing
Figure 36 Alternative 3-Wire Serial Control Timing A limited number of Readback addresses are provided to enable ALC operation to be monitored and to establish the identity and revision of the device. REGISTER ADDRESS BIT LABEL CHIP_ID DEVICE_REVI SON DEFAULT DESCRIPTION Readback the CHIP ID Readback the DEVICE_REVISON
R0 15:0 Software Reset R1 Power Management 1 2:0
Table 56 Readback Registers
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2-WIRE SERIAL CONTROL MODE
Pre-Production
The WM8940 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8940). The WM8940 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8940, then the WM8940 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8940 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8940 has acknowledged a correct address, the controller sends the first byte of control data (B23 to B16, i.e. the WM8940 8 bit register address). The WM8940 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B15 to B8, i.e. the most significant 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends the third byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8940 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 37 2-Wire Serial Control Interface In 2-wire mode the WM8940 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8940 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
POWER SUPPLIES
The WM8940 requires four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A larger AVDD slightly improves audio quality. SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output drivers. SPKVDD can range from 2.5V to 3.6V. SPKVDD can be tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than AVDD, the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND.
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It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths.
RECOMMENDED POWER UP/DOWN SEQUENCE
In order to minimise output pop and click noise, it is recommended that the WM8940/WM8941 device is powered up and down using one of the following sequences:
Power Up: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Turn on external power supplies. Wait for supply voltages to settle. Reset internal registers to default state (software reset). Enable non-VMID derived bias generator (VMID_OP_EN = 1) and level shifters (LVLSHIFT_EN = 1). Enable DAC soft mute (DACMU = 1). Select Clock source to MCLK (CLKSEL = 0) and audio mode (Master or Slave). Enable Power on Bias Control (POB_CTRL = 1) and VMID soft start (SOFT_START = 1). Enable speaker outputs (SPKPEN = 1, SPKNEN = 1) and wait for outputs to settle. Set VMIDSEL[1:0] bits for 75k reference string impedance. Wait for the VMID supply to settle. *Note 2. Enable analogue amplifier bias control (BIASEN = 1) and VMID buffer (BUFIOEN = 1). *Notes 1 and 2. Disable Power on Bias Control (POB_CTRL = 0) and VMID soft start (SOFT_START = 0). Enable DAC (DACEN =1) and Speaker Mixer (SPKMIXEN = 1). Enable output of DAC to speaker mixer (DAC2SPK = 1). Disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB. Ramp up the SPKVOL using the following values: -27 dB, -21 dB, -15 dB, -13 dB, -11 dB, -9 dB, -8 dB, -7 dB, -6 dB, -5 dB, -4 dB, -3 dB, -2 dB, -1 dB, 0 dB. Disable DAC soft mute (DACMU = 0).
Power Down: 1. 2. 3. 4. 5. 6. 7. Enable DAC soft mute (DACMU = 1). Enable non-VMID derived bias generator (VMID_OP_EN = 1). Enable on Bias Control (POB_CTRL = 1). Disable analogue amplifier bias control (BIASEN = 0) and VMID (VMIDSEL[1:0] bits set to OFF). Enable Fast VMID Discharge (TOGGLE = 1) to discharge VMID capacitor. Wait for VMID capacitor to fully discharge. Enable speaker output mute (SPKMUTE = 1).
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8. 9. 10.
Pre-Production Disable DAC (DACEN = 0), speaker mixer (SPKMIX = 0), and speaker outputs (SPKPEN = 0 and SPKNEN = 0). Reset all registers to their default state (software reset). Turn off external power supply voltages.
Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID in a way that is controlled and predictable. Choose the value of VMIDSEL bits based on the startup time (VMIDSEL = 10 for the slowest startup, VMIDSEL = 11 for the fastest startup). Startup time is defined by the value of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID.
2.
In addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the PGAs to avoid any audible pops and clicks.
POWER MANAGEMENT
VMID
The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS R1 Power management 1 BIT 1:0 LABEL DEFAULT DESCRIPTION Reference string impedance to VMID pin (determines startup time): 00=off (open circuit) 01=75k 10=300k 11=2.5k (for fastest startup)
VMIDSEL 00
Table 57 VMID Impedance Control
BIASEN
REGISTER ADDRESS R1 Power management 1 3 BIT LABEL BIASEN DEFAULT 0 DESCRIPTION Analogue amplifier bias control 0=Disabled 1=Enabled
Table 58 BIASEN Control
ESTIMATED SUPPLY CURRENTS
When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD.
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Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT MONOEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL BOOSTEN INPPGAEN ADCEN MONOEN SPKPEN SPKNEN MONOMIXEN SPKMIXEN DACEN 0.2mA 1.4mA (with clocks applied) 0.5mA 0.3mA 0.1mA 10K=>0.3mA, less than 0.1mA for 100k/500k 0.2mA 0.2mA 2.6mA 0.2mA 1mA from SPKVDD 1mA from SPKVDD 0.2mA 0.2mA 1.8mA AVDD CURRENT (MILLIAMPS)
Table 59 AVDD Supply Current
POP MINIMISATION
Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8940. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to be enabled before VMID at start-up. This feature can be used to minimise pops. Once VMID is enabled and has stabilised, POBCTRL should be set to 0. Register SOFT_START is the enable bit for the VMID soft-start function. Setting the bit to 1 causes charging of the VMID decoupling cap to follow a soft-start profile which minimises pops. This softstart profile has minimal impact on VMID charge time. Fast VMID discharge is enabled using TOGGLE. Setting to 1 opens a low impedance discharge path from VMID to GND. This function can be used during power down to reduce the discharge time of the VMID decoupling cap. Must be set to 0 for normal operation.
REGISTER ADDRESS R7 Additional Control
BIT 6
LABEL POB_CTRL
DEFAULT 0
DESCRIPTION Power on Bias Control 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) VMID Soft Start 0=disabled 1=enabled Fast VMID Discharge 0=normal 1=enable (used during power-down)
5
SOFT_START
0
4
TOGGLE
0
Table 60 POP Minimisation Control
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ADDR SOTWARE RESET ON WRITE / CHIP ID ON READ 1000_1001_0100_0000 BUFIOEN VMIDSEL[1:0] 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0101_0000 0000_0000_0000_0000 0000_0001_0100_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 DACPOL 0000_0000_0000_0010 0000_0000_0000_0000 0000_0000_1111_1111 0 0 0 0 WL[1:0] DAC_LOOPBACK BCLKDIV[2:0] TOGGLE SR[2:0] GPIOPOL 0 0 DACVOL[7:0] 0 AMUTE GPIOSEL[2:0] AUTOINC 0 0 MCLKDIV[2:0] POB_CTRL SOFT_START 0 0 SOFTMUTE OPCLKDIV[1:0] 0 0 0 0 MS SLOWCLKEN WL8 DAC_COMP[1:0] ADC_LOOPBACK ADC_COMP[1:0] FMT[1:0] 0 0 0 0 MODE_GPIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL 0 0 0 0 0 0 0 0 0 0 LOUTR BCP FRAMEP DLRSWAP ALRSWAP 0 0 0 0 0 0 0 0 0 0 0 0 0 VMID_OP_EN LVLSHIFT_EN 0 0 0 MONOEN AUXEN 0 SPKNEN PLLEN 0 SPKPEN MICBEN BOOSTEN VBUFEN BIASEN 0 MONOMIXEN DEVICE_REVISION[2:0] INPPGAEN 0 ADCEN SPKMIXEN 0 DACEN
Register Name
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Default Value (Bin)
Dec
Hex
WM8940
0
00
Software Reset
1 2 3
01 02 03
Power management 1 Power management 2 Power management 3
0 0 0
0 0 0
4
04
Audio Interface
0
0
5
05
Companding control
0
0
REGISTER MAP
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0 HPFCUT[2:0] 0 ADCVOL[7:0] NF0_A0[13:0] NF0_A1[13:0] NF1_A0[13:0] NF1_A1[13:0] NF2_A0[13:0] NF2_A1[13:0] NF3_A0[13:0] NF3_A1[13:0] 0 LIMDCY[3:0] 0 LIMLVL[2:0] 0 0 0 0 0 0 0 0 0 0 LIMEN LIMATK[3:0] LIMBOOST[3:0] 0 0 0 0 0 0 0 0 0 0 HPFEN HPFAPP 0 0 ADCPOL 0000_0001_0000_0000 0000_0000_1111_1111 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0011_0010 0000_0000_0000_0000 ALCGAIN[5:0] 0 ALCHLD[3:0] ALCDCY[3:0] 0 PLL_POWERDO WN FRACEN 0 PLLK[17:9] 0 0 MICBVSEL 0 PGABOOST 0 0 0 INPPGAZC 0 0 0 0 0 0 0 0 0 0 INPPGAMUTE MICP2BOOSTVOL[2:0] 0 AUX2SPK 0 0 0 0 0 PLLK[8:0] 0 0 0 0 0 AUXMODE 0 0 AUX2INPPGA INPPGAVOL[5:0] 0 0 0 0 0 AUX2BOOSTVOL[2:0] TSDEN BYP2SPK VROI DAC2SPK 0 ALCZC MICN2INPPGA 0 0 MICP2INPPGA 0 0 0 0 NGEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALCMODE 0 0 0 0 0 0 ALCSEL 0 0 ALCMAX[2:0] ALCMIN[2:0] ALCLVL[3:0] ALCATK[3:0] NGTH[2:0] PLLN[3:0] PLLK[23:18] 0000_0000_0011_1000 0000_0000_0000_1011 0000_0000_0011_0010 0000_0000_0000_0000 0000_0000_0100_1000 0000_0000_0000_1100 0000_0000_1001_0011 0000_0000_1110_1001 0000_0000_0000_0000 0000_0000_0011_0000 0000_0000_0000_0010 0000_0000_0101_0000 0000_0000_0000_0000 0000_0000_0000_0010 0000_0000_0000_0000 PLL_PRESCALE[1:0] 0 0 0 0 0 0 0 0 0 0 SPKATTN 0 SPKZC MONOATTN SPKMUTE MONOMUTE 0 0 0 SPKVOL[5:0] AUX2MONO BYP2MONO DAC2MONO 0000_0000_0111_1001 0000_0000_0000_0000
6 7
06 07
Clock Gen control Additional control
0 0
0 0
8
08
GPIO Stuff
0
0
9 10
09 0A
Control Interface DAC Control
0 0
0 0
11
0B
DAC digital Vol
0
0
12
0C
Reserved
13 14
0D 0E
Reserved ADC Control
0
0
15
0F
ADC Digital Vol
0
0
16
10
Notch Filter 1
NF0_UP
NF0_EN
17
11
Notch Filter 2
NF0_UP
0
18
12
Notch Filter 3
NF1_UP
NF1_EN
19
13
Notch Filter 4
NF1_UP
0
20
14
Notch Filter 5
NF2_UP
NF2_EN
21
15
Notch Filter 6
NF2_UP
0
22
16
Notch Filter 7
NF3_UP
NF3_EN
23
17
Notch Filter 8
NF3_UP
NF3_LP
24
18
DAC Limiter 1
0
0
25
19
DAC Limiter 2
0
0
26
1A
Reserved
27
1B
Reserved
28
1C
Reserved
29
1D
Reserved
30
1E
Reserved
31
1F
Reserved
32
20
ALC control 1
33
21
ALC control 2
0
0
34
22
ALC control 3
0
0
35
23
Noise Gate
0
0
36
24
PLL N
0
0
37
25
PLL K 1
0
0
38
26
PLL K 2
0
0
39
27
PLL K 3
0
0
40
28
Reserved
0
0
41
29
Reserved
42
2A
ALC control 4
0
0
43 44
2B 2C
Reserved Input ctrl
0
0
45
2D
INP PGA gain ctrl
0
0
46
2E
Reserved
47
2F
ADC BOOST ctrl
0
0
48
30
Reserved
49 50
31 32
Output ctrl SPK mixer control
0 0
0 0
51
33
Reserved
52
34
Reserved
53 54
35 36
Reserved SPK volume ctrl
0
0
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37 38
Reserved MONO mixer control
0
0
Pre-Production
66
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REGISTER BITS BY ADDRESS
Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS 0 (00h) BIT [15:0] LABEL RESET / CHIP_ID DEFAULT N/A DESCRIPTION Writing to this register will apply a software reset. Reading from this register will return the device id Reserved Enables the non-VMID derived bias current generator Power without enabling the VMID buffer. This bit must be set Management to 1 if output amplifiers are to be enabled before VMID is active. Once VMID and VMID buffer are enabled this bit can be left set to 0 or left set to 1. Enable bit for the level shifters. 1 for normal operation, Power 0 for standby. Management Auxiliary input buffer enable 0 = OFF 1 = ON PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=Disabled 1=Enabled Readback from this register will return the device revision in this position Enable bit for the VMID buffer. The VMID buffer is used to maintain a buffered VMID voltage on all analogue input and output pins. 1. for normal operation 0. for standby (where inputs and outputs settle to GND). Reference string impedance to VMID pin: 00=off (open circuit) 01=75k 10=300k 11=2.5k Reserved Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Reserved Input microphone PGA enable 0 = disabled 1 = enabled Reserved ADC Enable Control 0 = ADC disabled 1 = ADC enabled Reserved Analogue to Digital Converter (ADC) Input Signal Path Input Boost Auxiliary Inputs REFER TO Resetting the Chip / Control Interface
1 (01h)
15:9 8 VMID_OP_EN
00 0
7 6
LVLSHIFT_EN AUXEN
0 0
5
PLLEN
0
Master Clock and Phase Locked Loop (PLL) Microphone Biasing Circuit Power Management Control Interface Enabling the Outputs
4
MICBEN
0
3
BIASEN
0
2:0 2
DEVICE_REVI SION BUFIOEN
000 0
1:0
VMIDSEL
00
Power Management
2 (02h)
15:5 4 BOOSTEN
000h 0
3 2 INPPGAEN
0 0
1 0 ADCEN
0 0
3 (03h)
15:8
00h
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REGISTER ADDRESS 7 BIT LABEL MONOEN DEFAULT 0 MONOOUT enable 0 = disabled 1 = enabled SPKOUTN enable 0 = disabled 1 = enabled SPKOUTP enable 0 = disabled 1 = enabled Mono Mixer Enable 0 = disabled 1 = enabled Speaker Mixer Enable 0 = disabled 1 = enabled Reserved DAC enable 0 = DAC disabled 1 = DAC enabled Reserved LOUTR control 0=normal 1=Input mono channel data output on left and right channels BCLK polarity 0=normal 1=inverted Frame clock polarity 0=normal 1=inverted DSP Mode control 1 = Configures the interface so that MSB is available st on 1 BCLK rising edge after FRAME rising edge 0 = Configures the interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Controls whether DAC data appears in `right' or `left' phases of FRAME clock: 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME DESCRIPTION
Pre-Production REFER TO Analogue Outputs
6
SPKNEN
0
Analogue Outputs
5
SPKPEN
0
Analogue Outputs
4 3
Reserved MONOMIXEN
0 0 Analogue Outputs
2
SPKMIXEN
0
Analogue Outputs
1 0 DACEN
0 0
Analogue Outputs
4 (04h)
15:10 9 LOUTR
00h 0
Digital Audio Interfaces
8
BCP
0
Digital Audio Interfaces Digital Audio Interfaces
7
FRAMEP
0
Digital Audio Interfaces
4:3
FMT
10
Digital Audio Interfaces
2
DLRSWAP
0
Digital Audio Interfaces
1
ALRSWAP
0
Digital Audio Interfaces
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Pre-Production REGISTER ADDRESS 0 5 (05h) 15:7 6 DAC_LOOPBA CK BIT LABEL DEFAULT 0 0000 0 Reserved Reserved Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC data input is fed directly into ADC data output. 8 Bit Word Length for companding 0=Word Length controlled by WL 1=8 bits DAC companding 00=off 01=reserved 10=-law 11=A-law ADC companding 00=off 01=reserved 10=-law 11=A-law Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Reserved Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) Reserved DESCRIPTION
WM8940
REFER TO
Digital Audio Interfaces
5
WL8
0
Digital Audio Interfaces Digital Audio Interfaces
4:3
DAC_COMP
00
2:1
ADC_COMP
00
Digital Audio Interfaces
0
ADC_LOOPBA CK
0
Digital Audio Interfaces
6 (06h)
15:9 8 CLKSEL
00h 1
Digital Audio Interfaces
7:5
MCLKDIV
010
Digital Audio Interfaces
4:2
BCLKDIV
000
Digital Audio Interfaces
1 0 MS
0 0
Digital Audio Interfaces
7 (07h)
15:7
00000
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REGISTER ADDRESS 6 BIT LABEL POB_CTRL DEFAULT 0 DESCRIPTION Power on Bias Control 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) VMID Soft Start 0=disabled 1=enabled Fast VMID Discharge 0=normal 1=enable (used during powerdown) Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Enables the Timeout Clock for zero cross detection. Reserved Selects MODE as a GPIO pin 0 = MODE is an input. MODE selects 2-wire mode when low and 3-wire mode when high. 1 = MODE can be an input or output under the control of the GPIO control register. Interface operates in 3wire mode regardless of what happens on the MODE pin. 6 5:4 OPCLKDIV 0 00 Reserved PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIO Polarity invert 0=Non inverted 1=Inverted CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved Reserved AUTOINC 1 Auto-Incremental write enable 0=Auto-Incremental writes disabled 1=Auto-Incremental writes enabled Reserved Reserved
Pre-Production REFER TO POP Minimisation
5
SOFT_START
0
POP Minimisation
4
TOGGLE
0
POP Minimisation
3:1
SR
000
Audio Sample Rates
0 8 (08h) 15:8 7
SLOWCLKEN
0 00h
Zero Cross Timeout Control Interface
MODE_GPIO
0
General Purpose Input Output
3
GPIOPOL
0
General Purpose Input Output General Purpose Input Output
2:0
GPIOSEL
000
9 (09h)
15:2 1
Control Interface
0 10 (0Ah) 15:7
0 00
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Pre-Production REGISTER ADDRESS 6 BIT LABEL DACMU DEFAULT 0 DESCRIPTION DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled Reserved DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled Reserved DAC Polarity Invert 0 = No inversion 1 = DAC output inverted Reserved DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved 00h HPFEN 1 Reserved High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 14 for details. Reserved ADC Polarity 0=normal 1=inverted Reserved ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
WM8940
REFER TO Output Signal Path
5:3 2 AMUTE
00 0
Output Signal Path
1 0 DACPOL
0 0
Output Signal Path
11 (0Bh)
15:8 7:0 DACVOL
00h 11111111
Output Signal Path
12 (0Ch) 13 (0Dh) 14 (0Eh)
15:0 15:0 15:9 8
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7
HPFAPP
0
6:4
HPFCUT
000
3:1 0 ADCPOL
00 0
15 (0Fh)
15:8 7:0 ADCVOL
00h 11111111
16 (10h)
15
NF0_UP
0
Notch filter 0 update. The notch filter 0 values used Analogue to internally only update when one of the NF0_UP bits is Digital Converter set high. (ADC) Notch filter 0 enable: 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
14
NF0_EN
0
13:0
NF0_A0
0000h
Notch Filter 0 a0 coefficient
17 (11h)
15
NF0_UP
0
Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. Reserved
14
0
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WM8940
REGISTER ADDRESS BIT 13:0 LABEL NF0_A1 DEFAULT 0000h DESCRIPTION Notch Filter 0 a1 coefficient
Pre-Production REFER TO Analogue to Digital Converter (ADC)
18 (12h)
15
NF1_UP
0
Analogue to Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set Digital Converter (ADC) high. Notch Filter 1 enable. 0=Disabled 1=Enabled Notch Filter 1 a0 coefficient Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
14
NF1_EN
0
13:0
NF1_A0
0000h
19 (13h)
15
NF1_UP
0
Notch filter 1 update. The notch filter 1 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high. (ADC) Reserved Notch Filter 1 a1 coefficient Analogue to Digital Converter (ADC)
14 13:0 NF1_A1
0 0000h
20 (14h)
15
NF2_UP
0
Notch filter 2 update. The notch filter 2 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high. (ADC) Notch Filter 2 enable. 0=Disabled 1=Enabled Notch Filter 2 a0 coefficient Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
14
NF2_EN
0
13:0
NF2_A0
0000h
21 (15h)
15
NF2_UP
0
Notch filter 2 update. The notch filter 2 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high. (ADC) Reserved Notch Filter 2 a1 coefficient Analogue to Digital Converter (ADC)
14 13:0 NF2_A1
0 0000h
22 (16h)
15
NF3_UP
0
Notch filter 3 update. The notch filter 3 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high. (ADC) Notch Filter 3 enable. 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
14
NF3_EN
0
13:0
NF3_A0
0000h
Notch Filter 3 a0 coefficient
23 (17h)
15
NF3_UP
0
Notch filter 3 update. The notch filter 3 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high. (ADC) Notch Filter 3 mode select 0 = Notch Filter mode 1 = Low Pass Filter mode Notch Filter 3 a1 coefficient Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
14
NF3_LP
0
13:0
NF3_A1
0000h
24 (18h)
15:9
00h
Reserved
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Pre-Production REGISTER ADDRESS 8 BIT LABEL LIMEN DEFAULT 0 DESCRIPTION Enable the DAC digital limiter: 0=disabled 1=enabled 24 (18h) 7:4 LIMDCY 0011 DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 25 (19h) 15:7 6:4 LIMLVL 000h 000 Reserved
WM8940
REFER TO Output Signal Path Output Signal Path
Output Signal Path
Output Signal DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) Path 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB
3:0
LIMBOOST
0000
DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved
Output Signal Path
26 (1Ah) 27 (1Bh)
15:0 15:0
0000h 0000h
Reserved Reserved
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WM8940
REGISTER ADDRESS 28 (1Ch) 29 (1Dh) 30 (1Eh) 31(1Fh) 32 (20h) BIT 15:0 15:0 15:0 15:0 15:10 ALCGAIN [5:0] LABEL DEFAULT 0000h 0000h 0000h 0000h 000000 Reserved Reserved Reserved Reserved DESCRIPTION
Pre-Production REFER TO
Readback from this register will return the ALC gain in Input Limiter / this position Automatic Level Control (ALC) Reserved ALC function select 0=ALC disabled 1=ALC enabled Reserved Set Maximum Gain of PGA Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Input Limiter / Automatic Level Control (ALC)
9 8 ALCSEL
0 0
7:6 5:3 ALCMAX
00 111
2:0
ALCMIN
000
Set minimum gain of PGA
33 (21h)
15:8 7:4 ALCHLD
000h 000
Reserved ALC hold time before gain is increased.
3:0
ALCLVL
1011
ALC threshold level. Sets the desired signal level.
34 (22h)
15:9 8 ALCMODE
00h 0
Reserved Determines the ALC mode of operation: 0=Normal mode 1=Limiter mode. Decay (gain ramp-up) time
7:4
ALCDCY
0011
3:0
ALCATK
0010
ALC attack (gain ramp-down) time
35 (23h)
15:4 3 NGEN
000h 0
Reserved Noise gate function enable 1 = enable 0 = disable Noise gate threshold
2:0
NGTH
000
36 (24h)
15:8 7 PLL_POWERD OWN FRACEN
00h 0
Reserved PLL POWER 0=On 1=Off Fractional Divide within the PLL 0=Disabled (Lower Power) 1=Enabled 00 = MCLK input multiplied by 2 (default) 01 = MCLK input not divided (default) 10 = Divide MCLK by 2 before input to PLL 11 = Divide MCLK by 4 before input to PLL
6
1
5:4
PLLPRESCALE 00
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Pre-Production REGISTER ADDRESS BIT 3:0 LABEL PLLN[3:0] DEFAULT 1100 DESCRIPTION Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Reserved
WM8940
REFER TO Master Clock and Phase Locked Loop (PLL)
37 (25h)
15:6 5:0 PLLK[23:18]
000h 001100
Fractional (K) part of PLL1 input/output frequency ratio Master Clock and (treat as one 24-digit binary number). Phase Locked Loop (PLL) Reserved Fractional (K) part of PLL1 input/output frequency ratio Master Clock and (treat as one 24-digit binary number). Phase Locked Loop (PLL) Reserved Fractional (K) part of PLL1 input/output frequency ratio Master Clock and (treat as one 24-digit binary number). Phase Locked Loop (PLL) Reserved Reserved Reserved ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled Reserved Reserved Reserved Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD Reserved Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Input Signal Path Input Signal Path ALC Control 4
38 (26h)
15:9 8:0 PLLK[17:9]
00h 010010011
39 (27h)
15:9 8:0 PLLK[8:0]
00h 011101001
40 (28h) 41 (29h) 42 (2Ah)
15:0 15:0 15:2 1 ALCZC
0000h 0000h 0 0 (zero cross off) 0 0000h 00h MBVSEL 0
0 43 (2Bh) 44 (2Ch) 15:0 15:9 8
7:4 3 AUXMODE
0h 0
2
AUX2INPPGA
0
Input Signal Path
1
MICN2INPPGA
1
Input Signal Path
0
MICP2INPPGA
0
Connect input PGA amplifier positive terminal to MICP Input Signal Path or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Reserved Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path
45 (2Dh)
15:8 7 INPPGAZC
00h 0
6
INPPGAMUTE
1
Input Signal Path
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WM8940
REGISTER ADDRESS BIT 5:0 LABEL INPPGAVOL DEFAULT 010000 Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Reserved Reserved DESCRIPTION
Pre-Production REFER TO Input Signal Path
46 (2Eh) 47 (2Fh)
15:0 15:9 8 PGABOOST
0000h 00h 0
Input Boost Input Signal Path 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Reserved Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k uthorize Reserved Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Reserved Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of DAC to speaker mixer input 0 = not selected 1 = selected Reserved Reserved Reserved Analogue Outputs Analogue Outputs Output Switch Input Signal Path Input Signal Path
7 6:4
0 MICP2BOOSTVOL 000
3 2:0
0 AUX2BOOSTVOL 000
48 (30h) 49 (31h)
15:0 15:2 1 TSDEN
0000h 0000h 1
0
VROI
0
Analogue Outputs
50 (32h)
15:6 5 AUX2SPK
000h 0
4:2 1 BYP2SPK
000 0
0
DAC2SPK
0
Analogue Outputs
51 (33h) 52 (34h) 53 (35h)
15:0 15:0 15:0
0000h 0000h 0000h
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Pre-Production REGISTER ADDRESS 54 (36h) 8 BIT 15:9 SPKATTN LABEL DEFAULT 00h 0 Reserved Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB Reserved Reserved Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB DESCRIPTION
WM8940
REFER TO
Analogue Outputs
7
SPKZC
0
Analogue Outputs
6
SPKMUTE
1
Analogue Outputs
5:0
SPKVOL
111001
Analogue Outputs
55 (37h) 56 (38h)
15:0 15:8 7 MONOATTN
0000h 00h 0
Analogue Outputs
6
MONOMUTE
0
MONOOUT Mute Control Analogue Outputs 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Reserved Output of Auxiliary amplifier to mono mixer input: 0 = not selected 1 = selected Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Output of DAC to mono mixer input 0 = not selected 1 = selected Analogue Outputs
5:3 2 AUX2MONO
0 0
1
BYP2MONO
0
Analogue Outputs
0
DAC2MONO
0
Analogue Outputs
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WM8940 DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 61 Digital Filter Characteristics f > 0.546fs 0.546fs -55 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX
Pre-Production
UNIT
TERMINOLOGY
1. 2. 3. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See Table 62 for the total delay. PARAMETER Total Delay (ADC analogue input to digital audio interface output) Total Delay (Audio interface input to DAC analogue output) Table 62 Total Group Delay Notes 1. Wind noise filter is disabled. MIN 28/fs TYP 30/fs MAX 32/fs UNIT fs
33/fs
35/fs
37/fs
fs
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Pre-Production
WM8940
DAC FILTER RESPONSES
0.2
0 -20 Response (dB) -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 38 DAC Digital Filter Frequency Response
Figure 39 DAC Digital Filter Ripple
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
Response (dB)
0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
-40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
0
0.1
0.2 Frequency (Fs)
0.3
0.4
0.5
Figure 40 ADC Digital Filter Frequency Response
Figure 41 ADC Digital Filter Ripple
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WM8940
HIGHPASS FILTER
Pre-Production
The WM8940 has a selectable digital high pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency.
5 0 -5 -10 Response (dB)
10 0 -10 Response (dB)
0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
-15 -20 -25 -30 -35 -40
-20 -30 -40 -50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 42 ADC High pass Filter Response, HPFAPP=0
Figure 43 ADC High pass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown.
10 0 -10
Response (dB)
10 0 -10 -20 -30 -40 -50 -60
-20 Response (dB) -30 -40 -50 -60 -70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 44 ADC High pass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown.
Figure 45 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cutoff settings shown.
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Pre-Production
WM8940
The WM8940 supports four programmable notch filters. The fourth notch filter can be configured as a low pass filter. The following illustrates three digital notch filters, followed by a single low pass filter in the ADC filter path. Both the centre frequency and -3dB bandwidth are programmable for the notch filters. The cut off frequency is programmable for the low pass filter. The following graphs show the responses of 1) a single notch filter at three chosen centre frequencies, with three bandwidths for each, 2) the low pass filter at three chosen cut off frequencies and 3) the cascade of three notch filters followed by the low pass filter, each with a different centre / cut off frequency with three bandwidths for each.
NOTCH FILTERS AND LOW PASS FILTER
+0 -5 -10 -15 -20 -25
R E S P O N S E
(dB) -30 -35 -40 -45 -50 -55 -60 20
50
100
200
500
1k Frequency (Hz)
2k
5k
10k
20k
Figure 46 ADC Notch Filter Responses (48kHz); fc=100Hz, 1kHz, 10kHz; fb = 100Hz, 600Hz, 2kHz
+0 -5 -10 R E S P O N S E -15 -20 -25
T
(dB) -30 -35 -40 -45 -50 -55 -60 20
50
100
200
500
1k Frequency (Hz)
2k
5k
10k
20k
Figure 47 ADC Low Pass Filter Responses (48kHz); fc= 1kHz, 5kHz, 10kHz
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WM8940
Pre-Production
+0 -5 R E S P O N S E (dB) -10 -15 -20 -25 -30 -35 -40 20
T
50
100
200
500
1k Frequency (Hz)
2k
5k
10k
20k
Figure 48 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; NF2 fc = 10kHz; LPF fc = 11kHz; fb = 100Hz, 600Hz, 2kHz
NOTCH FILTER WORKED EXAMPLE
The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth. fc = 1000 Hz fb = 100 Hz fs = 48000 Hz
w 0 = 2fc / fs = 2 x (1000 / 48000) = 0.1308996939 rads w b = 2fb / fs = 2 x (100 / 48000) = 0.01308996939 rads
a0 =
1 - tan( w b / 2) 1 - tan(0.0130899693 9 / 2) = = 0.9869949627 1 + tan( w b / 2) 1 + tan( 0.0130899693 9 / 2)
a1 = -(1 + a0 ) cos( w 0 ) = -(1 + 0.9869949627 ) cos(0.1308996939 ) = -1.969995945
NFn_A0 = -a0 x 213 = -8085 (rounded to nearest whole number) NFn_A1 = -a1 x 212 = 8069 (rounded to nearest whole number)
These values are then converted to a 14-bit sign / magnitude notation:
NFn_A0[13] = 1; NFn_A0[12:0] = 13'h1F95; NFn_A0 = 14'h3F95 = 14'b11111110010101 NFn_A1[13] = 0; NFn_A1[12:0] = 13'h1F85; NFn_A1 = 14'h1F85 = 14'b01111110000101
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Pre-Production
WM8940
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 49
Recommended External Components
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WM8940 PACKAGE DIAGRAM
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DETAIL 1
D2 19 24 D
Pre-Production
DM035.C
18 EXPOSED GROUND 6 PADDLE
1 4 E2 INDEX AREA (D/2 X E/2) E
A
SEE DETAIL 2 13 6 2X 12 e 7 b 1 bbbM C A B 2X aaa C aaa C
TOP VIEW
BOTTOM VIEW
ccc C A3 A 0.08 C 5
DETAIL 1
DETAIL 2
45 degrees Datum
L L1
1
C
SEATING PLANE
SIDE VIEW
A1
DETAIL 2
0.32mm EXPOSED GROUND PADDLE e R
Terminal tip e/2
W T A3 H b Exposed lead G
Half etch tie bar
DETAIL 2
Symbols A A1 A3 b D D2 E E2 e G H L L1 T W aaa bbb ccc REF: MIN 0.80 0 0.18 2.00 2.00
Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.20 REF 1 0.25 0.30 4.00 2.15 4.00 2.15 0.50 BSC 0.213 0.1 0.40 0.1 0.2 2.25 2.25 2 2
0.30 0.03
0.50 0.15
7
Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-2.
NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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Pre-Production
WM8940
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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